`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:27:39 09/12/2012
// Design Name:   Timer
// Module Name:   C:/Users/Maria Victoria/workspace/projecto3/TimerTest.v
// Project Name:  projecto3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Timer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TimerTest;

	// Inputs
	reg [3:0] value;
	reg reset_i;
	reg clk1hz;
	reg clk_i;

	// Outputs
	wire expired;

	// Instantiate the Unit Under Test (UUT)
	Timer uut (
		.value(value), 
		.expired(expired), 
		.reset_i(reset_i), 
		.clk1hz(clk1hz), 
		.clk_i(clk_i)
	);

	initial begin
		// Initialize Inputs
		value = 1;
		reset_i = 0;
		clk1hz = 0;
		clk_i = 0;

	end
    always #20 clk_i= ~clk_i;
    always #220 clk1hz= ~clk1hz;
endmodule

